Read This! | Picolisp | Picolisp Machine | Pil Sources | Linux | BASH | C-Programmming | Javascipt | Python | Scheme | Operating Systems | AssemblyLanguage | Computer Security | Firewalls | Exploitation | Social Engineering | Metasploit | Emacs | vim | Pharo Smalltalk | Databases | Networking | Machine Learning | Git | Machine Learning | Algorithms

Notes on the Intel CPU Cache Architecture & Attacks

Caches on Intel CPU lecture @ media.ccc.de
Imagine a 4-core CPU, it usually has two caches per core which are private to the core and we have a Last Level Cache (LLC) which is divided into slices by how many cores you have.



Let us consider three instructions:

1. mov: accesses data in the main memory and from registers to registers
2. clflush: removes cache line from the cache
3. prefetch: prefetches cache line for future use

Data can reside in:

• CPU Registers
• Different Levels of Cache
• Main Memory
• Disk Storage

Flush and Reload - Cache Attack

• Attackers monitor the timing differences of memory access.
• The attack monitors which lines are accessed but not the content.
• the Attacker establishes a Covert Channel of communication between two processes. Which he would normally not be allowed to do so.

Prime & Probe - Cache Attack

Establish a Covert Channel

You need two apps on a phone for example. The apps will use the shared cache using the above to send info between the apps.

http:///wiki/?intelcpuarchitecture

15jun17

admin