Notes on the Intel CPU Cache Architecture & AttacksCaches on Intel CPU lecture @ media.ccc.de
Imagine a 4-core CPU, it usually has two caches per core which are private to the core and we have a Last Level Cache (LLC) which is divided into slices by how many cores you have.
Let us consider three instructions:
- mov: accesses data in the main memory and from registers to registers
- clflush: removes cache line from the cache
- prefetch: prefetches cache line for future use
- CPU Registers
- Different Levels of Cache
- Main Memory
- Disk Storage
Flush and Reload - Cache Attack
- Attackers monitor the timing differences of memory access.
- The attack monitors which lines are accessed but not the content.
- the Attacker establishes a Covert Channel of communication between two processes. Which he would normally not be allowed to do so.
Prime & Probe - Cache Attack
Establish a Covert ChannelYou need two apps on a phone for example. The apps will use the shared cache using the above to send info between the apps.